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Introduction to VHDL

Understand VHDL and how it is used to describe digital circuits
Instructor:
Your Embedded Systems Guy
826 students enrolled
English [Auto-generated]
Implement their own VHDL designs on a FPGA / CPLD
Interpret a digital design written in VHDL
Simulate their own VHDL designs

Introduction to VHDL is a course that someone with no experience or knowledge of VHDL can use to learn and understand the VHDL language. In this course students will learn about all of the different data types associated with the VHDL language. This course focuses on teaching students how the syntax of VHDL is interpreted and how it can be used to design circuits. There are over 8 different examples digital designs implemented in VHDL.

Course Structure

This course starts out by explaining the background and history of VHDL and it’s uses. Then students will learn about all the different objects and data types associated with VHDL. There are various examples showing the data types in use and how different objects behave in different applications. After learning about the data types and objects, students will then learn about the keywords and syntax of the VHDL language. Then students will learn about all of the different design architectures used in VHDL. Students will also learn how to design a test bench to simulate and verify functionality of their designs. This knowledge will then be used to complete the final project, tying in all facets of the VHDL language.

VHDL Designs

This course has many design examples, upon completing this course students will have their own library of VHDL design they can use and refer to at any time! This design library includes:

  • Logical AND gate
  • Logical OR gate
  • Logical NOR gate
  • Logical NAN gate
  • Logical XOR gate
  • Half Adder
  • Full Adder
  • D Flip-Flop
  • Digital Comparator
  • SR (Set Reset) Latch
  • 2:1 Multiplexer
  • Priority Encoder

Final Project

The final project in the course has students go through the design process of implementing a priority encoder on their very own development board. This project takes students through the various phases of developing a digital design, testing it, and implementing it. Students will be taken through step-by-step everything that is required to get the priority encoder up and running on their development board.

Feel free to message me with any questions before signing up for this course!

Introduction

1
Welcome to the Course

In this lecture I introduce myself as well as what you can expect to learn from this course.

2
Background

This lecture discusses the background of VHDL and ways it can be used.

3
VHDL Usage Example 1 - Circuit Simulation

This lecture shows an example of a way in which you can use VHDL, to simulate digital circuits.

Objects

1
Objects

This lecture introduces the concept of VHDL objects amd the various objects that are used in the VHDL language.

2
Signals

This lecture discusses and explains what signals are in the VHDL language.

3
Signal Example

This lecture gives an example of how signals are used in VHDL.

4
Variables

This lecture discusses variables and how they are used in the VHDL language.

5
VHDL Variable Example

This lecture gives an example of VHDL variables being used.

6
Constants

This lecture covers constants in the VHDL language and gives an example of how to use them.

7
Files

This lecture discusses how files can be used in VHDL.

Data Types

1
Standard Logic 1164

This lecture talks about the standard logic 1164 package and the data types and operations it supports.

2
Standard Logic Text IO Package

This lecture talks about the standard logic text IO package and the operations it supports.

3
Standard Logic Arithmetic

This lecture discusses the standard logic arithmetic package.

4
Numeric Bit

This lecture describes and explains how the Numeric Bit package is used in VHDL.

Loops and Statements

1
IF Statement

This lecture discusses the format of IF statements in VHDL and how they are processed.

2
CASE Statement

This lecture discusses how CASE Statements are used in VHDL and how they are processed.

3
LOOP Statement

This lecture explains two common loops used in VHDL:

  • While Loops
  • For Loops

Examples are given to show how these loops are constructed and operate.

4
NEXT Statement

This lecture explains how the NEXT statement is used in the VHDL language.

5
EXIT Statement

This lecture explains the VHDL EXIT statement and gives examples of the the EXIT statement being used.

Design Structure

1
Entity Example 1 - Digital Logic Circuit

This lecture shows an example of defining an entity in VHDL. This examples uses a digital logic circuit as an example.

2
Entity Example 2 - Multiplexer

This lecture walks through the steps of defining an entity for a multiplexer.

3
Architecture Example 1 - Digital Logic Circuit

This lecture walks through the example of defining the architecture of a digital logic circuit.

4
Architecture Example 2 - Multiplexer

This lecture walks through an example of defining the architecture for a multiplexer.

Data Flow Design Style

1
Logic Gate VHDL Implementations

This lecture shows examples of various logic gate implementations in VHDL, including:

  • AND gate
  • OR Gate
  • NAND Gate
  • NOR Gate
  • XOR Gate
  • XNOR Gate

Upon completing this lecture students will be gain a better understanding of how to implement a digital design using VHDL.

2
AND Gate VHDL Design

This lecture takes you through and shows step-by-step how to define an AND gate using VHDL.

3
OR Gate VHDL Design

This lecture takes you through and shows step-by-step how to define an AND gate using VHDL.

4
Half Adder Data Flow Design

In this lecture you will see step-by-step and line by line how a half adder is design in VHDL using a data flow style of architecture.

5
Full Adder Dataflow Design

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a data flow style of architecture.

Behavioral Design Style

1
Full Adder Behavioral Design

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a behavioral style of architecture.

2
D Flip-Flop Behavioral Design

In this lecture you will see step-by-step and line by line how a D flip-flop is design in VHDL using a behavioral style of architecture.

3
Comparator Behavioral Design

In this lecture you will see step-by-step and line by line how a comparator is designed in VHDL using a behavioral style of architecture.

Structural Design Style

1
Full Adder Structural Design

In this lecture you will see step-by-step and line by line how a full adder is design in VHDL using a structural style of architecture.

2
Set-Reset Latch Structural Design

In this lecture you will see step-by-step and line by line how a SR latch is designed in VHDL using a structural style of architecture.

3
2:1 Multiplexer Structural Design

This lecture walks through the entire design process for creating a 2:1 Multiplexer in VHDL. This design uses the structural style of architecture.

Test Bench Designs

1
Full Adder Test Bench Design

IN this lecture a full adder test bench is designed. This test bench is designed to be used with a simulator to simulate a full adder design.

2
D Flip-Flop Test Bench Design

This lecture walks through a test bench designed for a D flip-flop. This test bench is then designed to be used with a simulator to test the D flip-flop design.

Simulations

1
AND Gate ModelSim Simulation

This lecture walks through and shows how to simulate your AND gate VHDL design using ModelSim.

2
AND Gate Vivado Simulation

This lecture walks through and shows how to simulate your AND gate VHDL design using Vivado.

3
OR Gate ModelSim Simulation

This lecture walks through and shows how to simulate your OR gate VHDL design using ModelSim.

4
OR Gate Vivado Simulation

This lecture walks through and shows how to simulate your OR gate VHDL design using Vivado.

5
D-Flip Flop ModelSim Simulation

This lecture walks through and shows how to simulate your D flip-flop VHDL design using ModelSim.

6
D Flip-Flop Vivado Simulation

This lecture walks through and shows how to simulate your D flip-flop VHDL design using Vivado.

7
Full Adder ModelSim Simulation

This lecture walks through and shows how to simulate your full adder VHDL design using ModelSim.

8
Full Adder Vivado Simulation

This lecture walks through and shows how to simulate your full adder VHDL design using Vivado.

FPGA Development Flow Project Using VHDL

1
Priority Encoder VHDL Design

This lecture walks through the process of developing the priority encoder VHDL design.

2
Priority Encoder Test Bench Design

This lecture explains in detail how to design the priority encoder's test bench.

3
Priority Encoder Vivado Simulation

This lecture walks through the required steps to simulate the priority encoder in Vivado using the test bench you designed.

4
Priority Encoder IO Assignments

In this lecture we will assign the entity inputs and outputs of our VHDL design to actual I/O pins on the FPGA on our development board.

5
Priority Encoder Synthesis and Implementation

In this step we verify our design is synthesizable and that we can implement our design on the selected FPGA.

6
Priority Encoder Generating Bitstream

In this lecture we generate the bit stream, which is the file that is loaded unto the FPGA to configure it.

7
Program and Configure Your FPGA

In this lecture I walk through the steps required to program your development board, I'm using a BASYS 3 in this example.

8
Test Design on the FPGA

In this lecture I show a demonstration of the priority encoder running on the BASYS 3 development board.

Conclusion

1
Appendix A: Reading VHDL BNF

This lecture explains how BNF (Backus–Naur Form) is used to describe the syntax of a programming language.

2
Conclusion

This lecture concludes the Introduction to VHDL course.

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