4.15 out of 5
373 reviews on Udemy

Learn Vivado from Top to Bottom – Your Complete Guide

The complete guide for implementing designs on Xilinx FPGAs using Vivado Design Suite, for beginners and advanced users
Your Embedded Systems Guy
1,837 students enrolled
English [Auto-generated]
Use Vivado confidently and proficiently.
Understand the steps required to take their FPGA design from start to finish.
Implement a micro blaze softcore processor on their FPGA.
Generate HDL designs from c based code, using Vivado’s high level synthesis tool.

The Vivado design suite is the set of tools provided by Xilinx and is used to design, program, and debug Xilinx’s line of FPGAs. This course covers all of the different aspects and capabilities of the Vivado design suite. This course covers everything from the very basics to the more complex topics. This course is designed so that the student who has no experience with Vivado can take the course by starting with the very basics topics such as creating projects and design files. There are also more advanced topics so that the experienced student can learn things like how to create and program a soft core processor using the tools provided by Xilinx. This course covers many topics, including:

  • Downloading & Installing Vivado (I will be using a Windows machine, however you can install this on a Linux machine as well)
  • Creating Projects
  • Simulating Your Hardware Designs
  • Using Existing IP Cores
  • Creating & Managing Your Custom IP Cores
  • Creating and Programming a Micro Blaze soft core processor
  • Programming your Development Board
  • Automating Vivado Using Tool Command Line (tcl) Scripts
  • Creating Your Own Design Constraints
  • Converting Your C Code to a Hardware Design

Vivado contains many tools and this course will cover all of them, including:

  • Vivado’s Hardware Manager – This is used to load the hardware designs onto the FPGA or on board memory.
  • Vivado’s Simulator – This is what is used to simulate and verify that your design is working as expected.
  • Integrated Logic Analyzer (ILA)– This is used to act as a virtual oscilloscope while your design is running on the actual hardware target.
  • Vivado’s High Level Synthesis – This tool read C based code and converts it to a HDL based design.
  • Xilinx’s Software Development Kit (SDK) – This is the tool used to write C code that will run on the soft core processor implemented on the FPGA.

This course is laid out in such a way that each section takes on a specific topic or tool associated with Vivado. There are downloadable files that will have the students interact with Vivado so that they can get a hands on learning experience. The students will complete a hardware design project that will take them through all of the design steps neccasary so that they can start implementing their own idea’s on Xilinx FPGAs using Vivado Design Suite. Vivado is a very powerful tool that has a lot to offer and this course is designed to help aid you in learning how to use this powerful tool.


Welcome to the Course

This lecture introduces the course and explains everything that will be covered. This lecture also explains the course layout and what you can expect from this course.

Introduction to the Vivado Tool Suite

This lecture introduces the Vivado Tool Suite and gives a quick summary of its capabilities.

Vivado Download and Installation

In this lecture you will see step-by-step how to download and install the Vivado design suite on your computer.

Supported FPGAs and Development Boards

This lecture discusses the development boards and FPGA’s that are currently supported by Vivado.

Vivado Basics

Opening Vivado

This lecture explains what you will see when you open Vivado for the first time.

Creating a New Project in Vivado

This lecture will walk you through step-by-step on how to create a RTL project in Vivado. RTL projects are what we use to create designs we want to implement on the FPGA.

Importing a Xilinx ISE Project Into Vivado

If there is a project that someone sends you that they created in Xilinx ISE, this lecture explains how to import that project and work on it inside of Vivado.

Create a Project From a Predefined Template

This lecture walks through and shows students how to create a new project that is based off a predefined Vivado template.

Vivado Example Project

This lecture shows how to access the example projects in Vivado. These projects are very useful for looking around and getting a better understanding of what can all be accomplished in Vivado.

Add Existing Files to a Project

This lecture will walk you through how to add existing design files to your project. This is useful if you are developing the design in a separate program or received a design from someone else.

Creating New Files

This lecture walks through the steps of creating new design files, simulation files, constraints files, etc… 

Working with Block Designs in Vivado

In this lecture Vivado block designs are introduced and explained. You will walk through how to create them as well as use them to create your designs.

Generating the FPGA Configuration File

This lecture walks you through the required steps to create a bit stream file. This file is what is loaded onto your FPGA in order to configure it to operate as specified by your design.

Programming Your Development Board

This lecture shows where to find the FPGA configuration file and how to use Vivado’s Hardware Manager to locate and program your development board.

Documentation Navigator

This lecture introduces Xilinx’s document navigator. Xilinx documentation navigator is an extremely powerful tool that allows you to find the most up to date documentation regarding all kinds of HDL/device specific topics.

Pin Planning Tool

I/O Pin Planning Tool Introduction

This lecture introduces Vivado’s pin planning tool and explains ways in which it can be used.

Create an I/O Pin Planning Project

In this lecture students are shown step-by-step how to create a pin planning project in Vivado.

Create and Place I/O Ports

This lecture shows students how to create I/O ports and to place them on specific pins.

Perform a Design Rules Check

This lecture walks through the steps required to perform a design rules check on the pin placement selections.

Report Simultaneous Switching Noise SSN

This lecture shows how to check for simultaneous switching noise based on your pin placements.

Generate Contraints File and Top Level HDL File

In this lecture I will show you how to generate a constraints file based off your pin placement selections. I also will show you how this tool can create the top level HDL file for your design.

Intellectual Property (IP) Cores

Introduction to IP Cores

In this lecture I will explain what an IP core is and how they are used when developing hardware. 

Using IP Cores

In this lecture I will give a quick demonstration of why one would want to use IP cores over traditional Hardware Descriptive Language (HDL) programming.

Create IP Cores from a Specific Directory

This lecture shows step by step how to take hardware design files inside your Vivado project and turn them into IP cores. These IP cores can be placed in a block design inside Vivado.

Create IP Cores from a Block Design

This lecture explains how to create a custom IP core from a block design inside your Vivado project. This IP core can be saved into your custom IP core repository to be used again and again.

AXI Interface Explained

This lecture introduces the AXI interface and how it is used. We will use the AXI interface so that our IP cores can be controlled by the Micro Blaze softcore processor. We will actually use AXI IP cores in the “Working with Softcore Processor” section.

Create an AXI IP Core Peripheral Step 1

This lecture explains how to create an AXI IP core so that you can interface your IP core with a Micro Blaze soft core processor. The AXI IP cores can also be interfaced with the hard ARM cores located on Xillinx’s System on Chip (SoC) such as the Zynq.

Creating an AXI IP Core Peripheral - Step 2

This lectures walks through the steps of interfacing your HDL design with the AXI IP core generated HDL files.

Create an AXI IP Core Peripheral Step 3

This lecture walks through the steps of locating and placing your custom IP core with an AXI interface.

Customizing IP Cores

This lectures shows students how they can customize their IP cores. This lecture also shows how to attach a PDF document to their IP Core.

Creating a Custom IP Core Repository

In this lecture I will walk through the steps required to create your own IP core repository. These custom IP Core repositories are nice because you can then reuse your designs from various projects.

IP Core Repository Directory Structure

This lecture suggests different ways you can structure your IP core repository so that as you add more and more IP cores you can still stay organized.

Adding IP Cores to Your Repository

At this point you know how to create your own IP cores from a block design, a specific directory, as well as creating IP cores with an AXI interface. In this lecture I am going to show you how to add IP cores to a specific repository.

Adding a Custom IP Core Repository to a Vivado Project

This lecture walks through the steps in how to add a IP core to your custom directory.

Managing a Custom IP Core Repository

This lecture talks about the types of maintenance that is required for an IP repository.

IP Core Design Examples

Configure Internal FPGA Block RAM (BRAM)

This lecture shows step-by-step how to customize and initialize the FPGA’s internal block RAM using IP cores available through Vivado.

Xilinx Memory Interface Generator (MIG) IP Core

This lecture walks through the steps required to generate an external memory interface for your design. This is very useful when you plan on implementing a softcore processor or other memory heavy design.

Connecting Multiple AXI Peripherals to a Single Master

When working with large designs and integrating soft/hard core processors, multiple AXI IP cores will likely be used. This lecture shows how to connect multiple of these IP cores to a single AXI master, which is usually a processor.

Using Vivado's Connection Automation and Regerating Block Design Layouts

Vivado has a neat tool that is useful for increasing productivity as well as keeping your block designs clean. In this lecture you will be shown how to utilize Vivado’s auto-router and regenerate your block designs.

Working with Design Constraints

What are Design Constraints

This is an introduction to design constraints, it explains what they are, were and how they are used. This lecture also explains what will be covered in this section.

Applying I/O Constraints

This lecture shows how to add I/O constraints to your design. I/O constraints include the logic level, physical pin location, as well as the type of signal implemented on the specified pin.

Creating Clock Constraints

Complex designs typically require multiple clocks running at different frequencies. This lecture shows how to add new clocks to your design at various frequencies.

Automating Vivado

TCL Script Introduction

This lecture walks through and introduces as well as explains what a TCL script is and does. This is a powerful skillset to have as many other engineering tools use TCL scripts.

Build a Vivado Project Using TCL Scripts

There are several ways to create a project in Vivado, the most straightforward being to use the new project wizard. However, if you are creating a lot of projects and they all are using the same parts / settings then creating a custom TCL will save a lot of time. In this lecture you will be shown step-by-step how to use TCL scripts to create a Vivado Project.

Populate a Block Design Using TCL Scripts

This lecture shows how to create a block design, add IP cores to the newly created block design, and connect the IP cores all from a TCL script. These TCL scripts can be used again and again throughout different projects.

Using TCL Scripts in Your Custom IP Core

This lecture will show how to add custom TCL scripts to your IP core. These TCL scripts can then be used to add further customization to your IP cores.

How to Create Your Own Custom TCL Scripts

When working with revision control software its ideal to have the smallest file sizes possible. Instead of checking in entire projects and generated files, it’s possible to only check in TCL scripts and source files. This lecture will show you how to generate a TCL script that will re-generate your project and block design.

Hardware Design Debugging and Verification

Creating Simulation Files (Test Benches)

This lecture discusses the required format of a test bench file for use in the Vivado Tool Suite. There are several example test benches included as well.

Simulating Your Designs in Vivado

In this lecture a step-by-step example is shown on how to simulate your design using Vivado’s internal simulation tool. This is a very powerful tool that can be used when trying to debug and verify your design prior to the actual implementation.

Modifying the Simulation Waveform

This lectures shows ways to manipulate the simulated waveform for analysis. There are step-by-steps showing how to do the following:

- Zooming in/out or to a specific region
- Measuring time between signal edges
- Adding waves to the window
- Saving a waveform configuration file
- Change the format of a signal (radix)

Forcing Signal Values for Simulation

While your troubleshooting / simulating your design using Vivado’s simulator you may need to generate inputs without having to modify the test bench. This lecture shows how to force an input or internal signal to a specified value to help aid in the debugging process.

Vivado Debugging Tools Introduction

This lecture explains the different tools provided in the Vivado Tool Suite that are available to help you debug and verify that your design is working properly. Debugging hardware design is extremely challenging, but Vivado has some very powerful tools available to help you test and verify your design.

How to Use the Integrated Logic Analyzer (ILA) Core for Debugging

The Integrated Logic Analyzer Core is a logic analyzer that resides in your FPGA design while running. This core has many capabilities that an external logic analyzer would contain as well. In this lecture I am going to show you how to use the ILA debugging core.

How to Use the Virtual I/O (VIO) Core for Debugging

The virtual I/O core is very useful for debugging designs; it can be used to see what is happening while your design is running. This is very useful because there are occasions when your simulation works but your design does not. In this lecture I am going to show you how to use the VIO debugging core.

Working with Soft Core Processors

Creating Your First Softcore Processor Project

In this lecture we walk through the steps of creating a softcore processor project in Vivado. We will be using the MicroBlaze softcore processor.

Add AXI Peripherals to Your MicroBlaze Processor

This lecture walks through the steps of creating a basic softcore processor project. In this example we will be instantiating a MicroBlaze softcore processor in our FPGA. 

High Level Synthesis Tool

High Level Synthesis Tool Introduction

This lecture introduces Vivado’s High Level Synthesis tool, which is used to turn functional c code into a HDL design. This is a very powerful tool which can greatly speed up your development time. 

Programming the FPGA

Vivado Hardware Manager Introduction

This lecture introduces Vivado’s hardware manager. The hardware manager is the tool we will be using to program the FPGAs.

Prior to Programming Checklist

This is a checklist of things that need to be verified before attempting to load the configuration file onto the FPGA.

Loading the Configuration File on the FPGA

This lecture shows step-by-step how to load the .bit configuration file unto the FPGA via JTAG from Vivado’s Hardware Manager. 

Project Design Flow Example Using Vivado

Project Design Flow Walkthrough

This lecture introduces the project design section. In this lecture the following lectures are explained as well as what the project is.

Step 1 - Acquire Project Requirements

This lecture lists out the project requirements to successfully complete this project.

Step 2 - Select FPGA Based on Requirements

This lecture discusses the process of selecting an FPGA based on a set of requirements.

Step 3 - Create Project in Vivado

Once the device has been selected a project must be created. This steps walks through the process of creating a project based on the device selected.

Step 4 - Add Existing / Custom IP

In this step we will be adding the IP cores we are using to implement our final project. This can be as simple as making sure your custom IP repository contains the desired IP cores. 

Step 5 - Add / Create Design Constraints

In this step we will be creating / editing the constraints file we need for our final project.

Step 6 - Simulate and Verify Design

A very important step in the design process is to simulate your design. In this step we will be simulating our final project design.

Step 7 - Generate the FPGA Configuration File

Once we are confident our design is working correctly we need to generate the FPGA configuration file. This lecture will show how to generate the configuration file.

Step 8 – Program your Board to Verify Functionality

The final step to complete our design is that we want to program our board and verify that the design is working as we expect. In this lecture we will walk through the steps to program your FPGA using Vivado’s Hardware Manager.



A complete review of everything students have covered in this course.

You can view and review the lecture materials indefinitely, like an on-demand channel.
Definitely! If you have an internet connection, courses on Udemy are available on any device at any time. If you don't have an internet connection, some instructors also let their students download course lectures. That's up to the instructor though, so make sure you get on their good side!
4.2 out of 5
373 Ratings

Detailed Rating

Stars 5
Stars 4
Stars 3
Stars 2
Stars 1
30-Day Money-Back Guarantee


4 hours on-demand video
12 articles
Full lifetime access
Access on mobile and TV
Certificate of Completion